1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor, and more particularly to a semiconductor device including a CMOSFET made up of an NMOSFET and a PMOSFET formed on a silicon substrate, and a manufacturing method therefor.
2. Background Art
In recent years, the integration density of semiconductor integrated circuit devices has considerably increased. As such, devices such as transistors in MOS (Metal Oxide Semiconductor) devices have been miniaturized and enhanced in performance. Especially, gate dielectric films, which are a component of the MOS structure, have become thinner and thinner to accommodate the miniaturization, high-speed operation, and lower-voltage operation of the transistors.
Conventionally, a silicon oxide (SiO2) film or a silicon oxynitride (SiON) film is used as a gate dielectric film. However, reducing the film thickness of a gate dielectric film formed of such a material increases the leakage current.
On the other hand, the sub-0.1 μm generation CMOS (Complementary Metal Oxide Semiconductor) devices must employ gate dielectric films having an equivalent oxide thickness of 1.5 nm or less. Therefore, it is proposed that metal oxide films or metal silicate films, which have a high relative permittivity, may be used as the gate dielectric films to provide an increased film thickness and thereby reduce the leakage current.
A description will be given below of a conventional method for manufacturing a semiconductor device using high dielectric constant films as its gate dielectric films.
First of all, as shown in FIG. 30A, a silicon oxide film is buried in predetermined regions of a silicon substrate 301 to form device isolation regions 302 having an STI (Shallow Trench Isolation) structure and a sacrificial oxide film 303.
Then, as shown in FIG. 30B, P (phosphorus) is ion-implanted in the silicon substrate 301 using a resist 304 as a mask. The P implantation is repeated a plurality of times to form a diffusion layer and adjust the transistor threshold voltage. After the above P implantation process, the resist 304 is removed. Then, B (boron) is implanted in the silicon substrate 301 in the same manner as described above using another resist (now shown) as a mask. After removing the resist, a heat treatment is carried out to diffuse the impurities, forming an n-type diffusion layer 306 and a p-type diffusion layer 307, as shown in FIG. 30C.
After forming the diffusion layers, the sacrificial oxide film 303 is removed using an aqueous solution of NH4F. Then, a thin silicon oxide film 308 is formed on the surface of the silicon substrate 301, and a hafnium silicon oxynitride film 309 is formed on the silicon oxide film 308, as shown in FIG. 31A. Specifically, the hafnium silicon oxynitride film 309 may be formed by forming a hafnium silicide film on the silicon oxide film 308 and then heat-treating the substrate in an atmosphere of NH3 or N2 plasma.
Then, after forming an amorphous silicon film 3010 by a CVD (Chemical Vapor Deposition) technique, P is ion-implanted using a resist 3011 as a mask to form an n-type gate electrode, as shown in FIG. 31B. It should be noted that a polysilicon film may be formed instead of the amorphous silicon film 3010.
After removing the resist 3011, B (boron) ions are implanted in the amorphous silicon film 3010 in the same manner as described above using another resist (not shown) as a mask to form a p-type electrode. After removing the resist, a silicon oxide film 3013 is formed on the entire surface and processed using a resist 3014 as a mask, as shown in FIG. 31C. In FIG. 31C, reference numerals 3010a and 3010b denote the resultant n-type and p-type amorphous silicon films, respectively.
Then, as shown in FIG. 32A, after removing the resist 3014, the n-type amorphous silicon 3010a and the p-type amorphous silicon film 3010b are processed to form gate electrodes. After that, the hafnium silicon oxynitride film 309 and silicon oxide film 308 are etched using the silicon oxide film 3013 as a hard mask such that portions of the gate dielectric film (made up of the hafnium silicon oxynitride film 309 and silicon oxide film 308) other than those under the gate electrodes are removed, as shown in FIG. 32B. It should be noted that the silicon oxide film 3013 is also etched off (or removed by etching) at that time.
After that, the sides of the gate electrodes 3010a and 3010b are slightly oxidized at a temperature between 900° C. and 1,000° C. in an atmosphere containing a concentration of oxygen between 0.05% and 1%, and then a silicon oxide film 3015 is deposited on the entire surface, as shown in FIG. 32C.
Then, B is ion-implanted in the n-type diffusion layer 306 using a resist 3016 and the gate electrode 3010b as masks, as shown in FIG. 33A. After that, P is ion-implanted in the p-type diffusion layer 307 in the same manner. This forms a p-type extension region 3018 and an n-type extension region 3019, as shown in FIG. 33B.
Then, as shown in FIG. 33C, a silicon nitride film 3020 is formed on the entire surface by a CVD technique. After that, reactive ion etching is carried out to remove portions of the silicon oxide film 3015 and the silicon nitride film 3020 other than those on the sides of the gate electrodes 3010a and 3010b. 
Then, as shown in FIG. 34A, B is ion-implanted in the n-type diffusion layer 306 using as masks a resist 3021 and the gate electrode 3010b (with the sidewalls formed of remaining portions of the silicon oxide film 3015 and the silicon nitride film 3020). After removing the resist 3021, P is ion-implanted in the p-type diffusion layer 307 in the same manner. Then, a heat treatment is carried out at a temperature between 900° C. and 1,100° C. to activate the impurities, forming a p-type source/drain diffusion layer 3023 and an n-type source/drain diffusion layer 3024, as shown in FIG. 34B.
Then, a nickel film (not shown) and a titanium nitride film (not shown) are formed on the entire surface, and a heat treatment is carried out. After that, the titanium nitride film and the unreacted portion of the nickel film are etched off (removed by etching) so as to selectively form a nickel silicide film 3025 only on the source/drain diffusion layers 3023 and 3024 and the silicon gate electrodes 3010a and 3010b, as shown in FIG. 34C.
Then, an interlayer insulating film 3029 is formed and planarized by a CMP (Chemical Mechanical Polishing) technique, as shown in FIG. 35. After that, contacts, wiring, etc. are formed.
However, analysis of the characteristics of transistors formed by the above conventional method indicates that, whereas the NMOSFET (N-Channel Metal Oxide Semiconductor Field Effect Transistor) has an appropriate threshold voltage value, the PMOSFET (P-Channel Metal Oxide Semiconductor Field Effect Transistor) has its threshold voltage considerably shifted toward the negative side. Furthermore, the PMOSFET has a smaller inversion capacitance than the NMOSFET, making it impossible to ensure a desired drain current level (see, e.g., T. Aoyama et al., International Workshop on Gate Insulator, 2003, p. 174).
To prevent the threshold voltage from being shifted and to obtain a large inversion capacitance, attempts have been made to use metal, metal nitride, metal silicate, etc. for gate electrodes, instead of silicon. Different metals have different work functions. Therefore, since the threshold voltage of a transistor changes with the work function of the gate electrode, a metal having an optimum work function may be used for the gate electrode to control the threshold voltage (or optimize the threshold voltage). Further, a metal electrode is less likely to be depleted than a silicon electrode, allowing a large inversion capacitance to be obtained.
However, since metal electrodes have poor heat resistance as compared to silicon electrodes, it is not possible to form a transistor with metal electrodes using the above conventional process. That is, since the above method forms source/drain diffusion layers after forming gate electrodes, a heat treatment must be subsequently performed at approximately 1,000° C. to activate the impurities. Such a heat process changes the shape of the metal electrodes and causes impurities to diffuse into the gate dielectric films, etc. To overcome these problems, methods have been proposed which form source/drain diffusion layers before forming gate electrodes (see, e.g., A. Chatterjee et al., International Electron Devices Meeting (IEDM), 1997, p. 821; A. Yagishita et al., International Electron Devices Meeting (IEDM), 1998, p. 785).
One of these methods will be described below. It should be noted that the gate electrodes of the NMOSFET and the PMOSFET are assumed to be formed of the same type of metal film, for simplicity.
First, after forming device isolation regions 402 and a sacrificial oxide film 403 in a silicon substrate 401, P (phosphorus) and B (boron) are implanted in the substrate sequentially and then a heat treatment is carried to form an n-type diffusion layer 406 and a p-type diffusion layer 407, as in the steps shown in FIGS. 30A to 30C. After that, an amorphous silicon film 4010 is formed on the sacrificial oxide film 403 by a CVD technique, producing the structure shown in FIG. 36A. It should be noted that a polysilicon film may be formed instead of the amorphous silicon film 4010.
Then, a silicon oxide film 4013 is formed on the entire surface and processed using a resist 4014 as a mask, as shown in FIG. 36B. After removing the resist 4014, the amorphous silicon film 4010 is processed using the silicon oxide film 4013 as a mask, forming gate electrodes, as shown in FIG. 36C.
Then, the sides of the gate electrodes 4010 are slightly oxidized at a temperature between 900° C. and 1,000° C. in an atmosphere containing a concentration of oxygen between 0.05% and 1%, and a silicon oxide film 4015 is deposited on the entire surface. After that, B and P are ion-implanted in the n-type diffusion layer 406 and the p-type diffusion layer 407, respectively, using resists (not shown) and the gate electrodes 4010 as masks to form a p-type extension region 4018 and an n-type extension region 4019, as shown in FIG. 37A.
Then, after forming a silicon nitride film 4020 on the entire surface by a CVD technique, reactive ion etching is carried out to remove portions of the silicon oxide film 4015 and the silicon nitride film 4020 other than those on the sides of the gate electrodes 4010. After that, B is ion-implanted in the n-type diffusion layer 406 using as masks a resist 4021 and the (PMOS) gate electrode 4010 (with a silicon oxide film 4013 thereon and with the sidewalls formed of remaining portions of the silicon oxide film 4015 and the silicon nitride film 4020), as shown in FIG. 37B.
After removing the resist 4021, P is ion-implanted in the p-type diffusion layer 407 in the same manner. Then, a heat treatment is carried out at a temperature between 900° C. and 1,100° C. to activate the impurities, forming a p-type source/drain diffusion layer 4023 and an n-type source/drain diffusion layer 4024, as shown in FIG. 37C.
Then, portions of the sacrificial oxide film 403 other than those under the gate electrodes 4010 are removed using an aqueous solution of dilute hydrofluoric acid or NH4F. Then, a heat treatment is carried out after forming a nickel film and a titanium nitride film on the entire surface. After that, the titanium nitride film and the unreacted portion of the nickel film are etched off so as to selectively form a nickel silicide film 4025 only on the source/drain diffusion layers 4023 and 4024, as shown in FIG. 38A.
Then, an interlayer insulating film 4026 is formed by a CVD technique or a coating technique and polished by a CMP technique until the amorphous silicon films 4010 are exposed. After that, the exposed amorphous silicon films 4010 are removed by reactive ion etching, as shown in FIG. 38B.
Then, after removing the exposed sacrificial oxide film 403, a thin silicon oxide film 408 is formed on the surface of the silicon substrate 401, and then a hafnium silicate film 409 is formed on the entire surface as a high dielectric constant insulating film, as shown in FIG. 38C.
Then, a titanium nitride film 4030 and a tungsten film 4031 are deposited, and portions of the titanium film 4030 and the tungsten film 4031 other than those in the gate electrode portions (that is, the portions of the titanium 4030 and the tungsten film 4031 above the interlayer insulating film 4026) are removed by a CMP technique. Then, after removing the portion of the hafnium silicate film 409 on the interlayer insulating film 4026, an interlayer insulating film 4029 is deposited and planarized, as shown in FIG. 39. After that, contacts, wiring, etc. are formed.
However, if the gate electrodes of the NMOSFET and the PMOSFET are formed of the same type of metal film, the threshold voltage of one of the FETs cannot be set to an appropriate value. For example, assume that the electrodes are formed of a titanium nitride film, whose Fermi level lies close to the middle of the bandgap of silicon, and used with a high dielectric constant insulating film, as in the above example. In such a case, even though the PMOSFET has a threshold voltage value close to an appropriate value, the NMOSFET has its threshold voltage shifted toward the positive side, as compared to when silicon electrodes are used (see FIG. 29B). This problem arises not only with NMOS gate electrodes formed of a titanium nitride film but also with NMOS gate electrodes of other materials whose Fermi level lies close to the middle of the bandgap of silicon, such as nickel silicide and cobalt silicide, when these electrodes are used with a high dielectric constant insulating film. It should be noted that the above problem does not occur when gate electrodes of nickel silicide are used with a gate dielectric film formed of a silicon oxide film (see, e.g., W. P. Maszara et al., International Electron Devices Meeting (IEDM), 2002, p. 367; Z. Krivokapic et al., International Electron Devices Meeting (IEDM), 2002, p. 271). This means that this problem is considered to occur only when a high dielectric constant insulating film is used as a gate dielectric film.
To overcome the above problem, attempts have been made to employ a configuration in which the NMOSFET and the PMOSFET include metal gate electrodes having different work functions (see, e.g., Japanese Laid-Open Patent Publications Nos. 2000-252371, 2003-258121, and 2003-45995). Such an arrangement is expected to provide appropriate threshold voltage values and large inversion capacitances. However, since the metal electrodes of the NMOSFET and the PMOSFET are formed separately from each other, a larger number of manufacturing steps must be performed, resulting in increased cost. Further, the above conventional method forms the nickel silicide 4025 on the source/drain diffusion layers 4023 and 4024 before forming the gate dielectric films. In such a case, however, when the gate dielectric films are formed, the temperature must be maintained below 600° C., considering the aggregation resistance of nickel silicide. Thus, the heat process for the gate dielectric films must be performed at less than 600° C., making it difficult to improve the film quality of the gate dielectric films.
To avoid this problem, instead of the sacrificial oxide film 403, a high dielectric constant gate dielectric film, etc. may be formed beforehand. In such a case, sufficient heat treatment can be carried out when forming the gate dielectric films. However, when the silicon electrodes 4010, which are dummy gate electrodes, are etched off, the gate dielectric films may be damaged or removed together with silicon electrodes 4010.
The problems with the conventional techniques are summarized as follows.
If the gate dielectric films are formed of a high dielectric constant film and used with silicon electrodes, the threshold voltage of the PMOSFET shifts toward the negative side and the inversion capacitance is small.
Metal electrodes may be used to solve the above problems. Such an arrangement provides large inversion capacitances. However, it is necessary to form metal electrodes having work functions optimum for the NMOSFET and the PMOSFET, respectively. This means that these metal electrodes must be formed in separate steps, increasing the total number of manufacturing steps and hence increasing the cost. Furthermore, the source/drain diffusion layers must be formed before forming the (metal) gate electrodes, considering the heat resistance of the metal electrodes. However, since silicide formed on the surfaces of the source/drain diffusion layers has a low heat resistance, the substrate cannot be heat-treated at a high temperature when forming the gate dielectric films, making it difficult to improve the film quality of the gate dielectric films.
To avoid these problems, the gate dielectric films may be formed before forming the source/drain diffusion layers and the silicide on these layers. This method, however, is disadvantageous in that the gate dielectric films are damaged when the silicon electrodes, which are the dummy gate electrodes, are etched off. In this case, it might happen that the gate dielectric films themselves are etched.